1. Field of the Invention
The present invention is directed generally to a method and apparatus for transmitting and receiving data at a frequency greater than a clock signal and, more particularly, to a memory circuit and associated method for transmitting and receiving data at both the rising edge and the falling edge of the clock signal.
2. Description of the Background
Synchronous memory devices, such as static random access memory (SRAM) and dynamic random access memory (DRAM), are triggered by an externally supplied clock signal. Typically, access to the memory device is triggered once per clock cycle, at either the rising edge or the falling edge of the clock signal.
Architecture for a typical memory system includes not only the memory circuit itself, such as SRAM and DRAM, but also a processor for controlling the system and additional circuits for supporting operation of the system. For example, in a cache memory system the support circuits include a cache control logic and a TAG device for supporting the operation of the memory circuit. Regardless of the particular memory system, the prior art method of operating synchronous memory circuits is problematic when, for example, one component of the system, such as the memory device, cannot operate as quickly as another component of the system, such as the processor. For example, it may be desirable to run a Pentium.RTM. processor (manufactured by Intel, Corp., Santa Clara, Calif.) at 133 Megahertz, but it requires expensive memory circuits and associated logic that can also operate at 133 Megahertz. Significant monetary savings can be realized if slower, less expensive memory devices and associated logic, such as that which operates at 66 Megahertz, can be used with a 133 Megahertz processor.
Thus, the need exists for a memory system that can utilize a high speed processor with less expensive, lower speed memory devices and associated logic while still transferring data at the high speed of the processor. Furthermore, the need exists for a memory circuit for use in such a system to transmit data at twice the frequency of the clock signal.